The present invention relates to a data processing system having hierarchial memories, such as buffer memories of a plurality of central processing units, a main memory which cooperates with the central processing units, an intermediate buffer memory located between the central processing units and the main memory. More particularly the present invention relates to a system in which so-called move-in and move-out operations are achieved, between the intermediate buffer memory and the main memory, under a so-called swap control method, and, further, both the intermediate buffer memory and the main memory are controlled by a so-called set associative method, and, furthermore, the main memory itself is accessed under a so-called interleave control method.
Generally, in a large capacity memory, the main memory comprises of a plurality of memory apparatuses. Each of these memory apparatuses is called a bank or memory bank. A head address for a desired one of the banks is usually specified by one or more of the upper bits of address information. For example, if there are four banks in the main memory, the head address of the desired bank can be specified by two bits (4=2.sup.2) of the address information. Thus, one of the desired banks can be selected by using the upper bits of the address information.
On the other hand, in the above mentioned data processing system, since both the intermediate buffer memory and the main memory are controlled by the set associative method, it is necessary for the address information to specify one desired data set to be accessed by one of the central processing units. Usually, the set can be specified by so-called set address bits, other than one or more of said upper bits, which are contained in the address information.
As mentioned above, the desired data set to be accessed is specified by the address information, and said move-in and move-out operations are achieved by using the address information, in order to realize a swapping of data between the intermediate buffer memory and a main memory. In this case, it should be noted that the memory bank which stores data to be read, through the move-in operation from the main memory to the intermediate buffer memory, it not always the same as the bank which stores data to be written, through the move-out operation from the intermediate buffer memory to the main memory. If the bank in which the move-in operation is conducted, is always the same as the bank in which the move-out operation has been conducted during one step for executing a certain program, the process for achieving the management of the main memory will be simplified, and the operating speed of the main memory will be increased. Howeover, in the usual data processing system having hierarchical memories, it is difficult to simplify the above mentioned process used for achieving the management of the main memory, and also, the operating speed of the main memory cannot be increased. This is because, as previously mentioned, since a requirement, during a step, for occupying or using the memory bank often coincides with a requirement, during another step, for occupying the same bank, it is necessary to introduce a particular protocol in the system, by which protocol traffic control between these conflicting steps is performed.